Energy-efficient FPGA implementation for binomial option pricing using OpenCL

• Published in: 2014 Design, Automation & Test in Europe Conference & Exhibition (DATE) pp. 1 - 6
• Main Authors: Morales, Valentin Mena, Horrein, Pierre-Henri, Baghdadi, Amer, Hochapfel, Erik, Vaton, Sandrine
• Format: Conference Proceeding
• Language: English
• Published: EDAA 01.03.2014
• Subjects: Acceleration; Field programmable gate arrays; Hardware; Kernel; Power demand; Pricing; Random access memory
• ISSN: 1530-1591; 1558-1101
• DOI: 10.7873/DATE.2014.221

Energy efficiency of financial computations is a performance criterion that can no longer be dismissed, and is as crucial as raw acceleration and accuracy of the solution. In order to reduce the energy consumption of financial accelerators, FPGAs offer a good compromise with low power consumption and high parallelism. However, designing and prototyping an application on an FPGA-based platform are typically very time-consuming and requires significant skills in hardware design. This issue constitutes a major drawback with respect to software-centric acceleration platforms and approaches. A high-level approach has been chosen, using Altera's implementation of the OpenCL standard, to answer this issue. We present two FPGA implementations of the binomial option pricing model on American options. The results obtained on a Terasic DE4 - Stratix IV board form a solid basis to hold all the constraints necessary for a real world application. The best implementation can evaluate more than 2000 options/s with an average power of less than 20W.