A performance analysis of PIM, stream processing, and tiled processing on memory-intensive signal processing kernels

Trends in microprocessors of increasing die size and clock speed and decreasing feature sizes have fueled rapidly increasing performance. However, the limited improvements in DRAM latency and bandwidth and diminishing returns of increasing superscalar ILP and cache sizes have led to the proposal of...

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Bibliographic Details
Published in30th Annual International Symposium on Computer Architecture, 2003. Proceedings pp. 410 - 419
Main Authors Suh, J., Kim, E.-G., Crago, S.P., Lakshmi Srinivasan, French, M.C.
Format Conference Proceeding
LanguageEnglish
Published IEEE 2003
Subjects
Bandwidth
Beam steering
Clocks
Delay
Kernel
Microprocessors
Performance analysis
Pipeline processing
Random access memory
Signal processing
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Summary:Trends in microprocessors of increasing die size and clock speed and decreasing feature sizes have fueled rapidly increasing performance. However, the limited improvements in DRAM latency and bandwidth and diminishing returns of increasing superscalar ILP and cache sizes have led to the proposal of new microprocessor architectures that implement processor-in-memory, stream processing, and tiled processing. Each architecture is typically evaluated separately and compared to a baseline architecture. We evaluate the performance of processors that implement these architectures on a common set of signal processing kernels. The implementation results are compared with the measured performance of a conventional system based on the PowerPC with Altivec. The results show that these new processors show significant improvements over conventional systems and that each architecture has its own strengths and weaknesses.
ISBN:0769519458
9780769519456
ISSN:1063-6897
2575-713X
DOI:10.1109/ISCA.2003.1207018