A PLA based asynchronous micropipelining approach for subthreshold circuit design

Power consumption is a dominant issue in contemporary circuit design. Sub-threshold circuit design is an appealing means to dramatically reduce this power consumption. However, sub-threshold designs suffer from the drawback of being significantly slower than traditional designs. To reduce the speed...

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Bibliographic Details
Published in2006 43rd ACM/IEEE Design Automation Conference pp. 419 - 424
Main Authors Jayakuma, N., Garg, R., Gamache, B., Khatri, S.P.
Format Conference Proceeding
LanguageEnglish
Published IEEE 2006
Subjects
Asynchronous
Circuit synthesis
Delay
Design
Design engineering
Energy consumption
Integrated circuit synthesis
Micro-pipelining
Network synthesis
PLA
Power engineering computing
Programmable logic arrays
Protocols
Sub-threshold
Very large scale integration
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Summary:Power consumption is a dominant issue in contemporary circuit design. Sub-threshold circuit design is an appealing means to dramatically reduce this power consumption. However, sub-threshold designs suffer from the drawback of being significantly slower than traditional designs. To reduce the speed gap between sub-threshold and traditional designs, we propose a sub-threshold circuit design approach based on asynchronous micropipelining of a levelized network of PLAs. We describe the handshaking protocol, circuit design and logic synthesis issues in this context. Our preliminary results demonstrate that by using our approach, a design can be sped up by about 7times, with an area penalty of 47%. Further, our approach yields an energy improvement of about 4times, compared to a traditional network of PLA design. Our approach is quite general, and can be applied to traditional circuits as well
ISBN:1595933816
9781595933812
ISSN:0738-100X
DOI:10.1109/DAC.2006.229224