Highly linear upconverter MMIC designs with complete package and test board effects for CDMA applications

• Published in: IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, 2003 pp. 405 - 408
• Main Authors: Wu, J.M., Jau, J.K., Horng, T.S., Tu, C.C.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 2003
• Subjects: Foundries; Gallium arsenide; Heterojunction bipolar transistors; Linearity; MMICs; Multiaccess communication; Packaging; Radio frequency; Testing; Voltage
• ISBN: 0780376943; 9780780376946
• ISSN: 1529-2517; 2375-0995
• DOI: 10.1109/RFIC.2003.1213972

1.9 GHz upconverter MMICs are designed and implemented using GaAs HBT foundry process. A crucial goal for the design is to achieve the high linearity required in CDMA systems with low idle currents. In addition, complete package and test board effects need to be considered rigorously. The proposed design adopts a class-AB input stage in a Gilbert cell to enhance the linearity. Another design based on the conventional emitter degeneration technique is also implemented on the same chip for comparison. The chip is finally housed in a 24-pin bump-chip carrier (BCC) package and surface-mounted on a test board. Both RF and LO ports are internally matched to 50 /spl Omega/ on chip. A single supply voltage of 3V is used. The measured results show that with a reference input power of -10 dBm for IS-95 CDMA applications, the class-AB design achieves an adjacent channel power ratio (ACPR) of -44.9 dBc with a consumed current of 15 mA, while the emitter degeneration design achieves an ACPR of -43.8 dBc with a consumed current of 28.5 mA.. Package and test board effects are analyzed using the 3-D EM simulation tool and transformed into the equivalent-circuit elements. The simulation including package and test board effects can predict the measured results quite well.