An Integrated 60-GHz Front-end Receiver with a Frequency Tripler Using 0.13-μm CMOS Technology

• Published in: 2007 14th IEEE International Conference on Electronics, Circuits and Systems pp. 829 - 832
• Main Authors: Po-Hung Chen, Min-Chiao Chen, Chung-Yu Wu
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.12.2007
• Subjects: Circuits; CMOS technology; Energy consumption; Frequency; Millimeter wave technology; Noise figure; Parasitic capacitance; Performance gain; Phase locked loops; Signal generators
• ISBN: 142441377X; 9781424413775
• DOI: 10.1109/ICECS.2007.4511119

In this paper, a 60-GHz CMOS direct-conversion receiver integrated with a frequency tripler is proposed. The proposed receiver consists of a low-noise amplifier (LNA), a down-conversion mixer, output buffers, and a frequency tripler. This chip is designed using 0.13-um CMOS technology. By using a frequency tripler, the operating frequency of the PLL can be reduced from 60 GHz to 20 GHz. This makes the implementation of the PLL much easier. According to the simulation results, the receiver has a noise figure (NF) of 7.6 dB, a power gain of 29.2 dB. It consumes 14.2 mW from a 1.2- V power supply.