CMP-less integration of 40nm-gate totally silicided (TOSI) bulk transistors using selective S/D Si epitaxy and ultra-low gates

In this paper, we present an innovative way of fabricating CMOS transistors with totally Ni-silicided (Ni-TOSI) gates without using a CMP step before the full gate silicidation. The combination of the use of a hard-mask-capped ultra-low Si gate with a selective S/D epitaxy step enables us to obtain...

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Published inProceedings of 35th European Solid-State Device Research Conference, 2005. ESSDERC 2005 pp. 453 - 456
Main Authors Muller, M., Mondot, A., Aime, D., Froment, B., Talbot, A., Roux, J.-M., Ribes, G., Morand, Y., Descombes, S., Gouraud, P., Leverd, F., Pokrant, S., Toffoli, A., Skotnicki, T.
Format Conference Proceeding
LanguageEnglish
Published IEEE 2005
Subjects
Capacitance
Dielectrics
Electric breakdown
Epitaxial growth
Fabrication
Gate leakage
Implants
Impurities
MOS devices
Silicidation
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Summary:In this paper, we present an innovative way of fabricating CMOS transistors with totally Ni-silicided (Ni-TOSI) gates without using a CMP step before the full gate silicidation. The combination of the use of a hard-mask-capped ultra-low Si gate with a selective S/D epitaxy step enables us to obtain a well-behaved silicidation of the junctions and the full gate within one single step with minimal gate lengths of 40nm. Moreover, we show that the TOSI PMOS device performances are compatible with the 45nm-node LP requirements. Reliability data is added demonstrating that no additional breakdown mechanisms occur after the TOSI process.
ISBN:0780392035
9780780392038
ISSN:1930-8876
DOI:10.1109/ESSDER.2005.1546682