Bit line coupling scheme and electrical fuse circuit for reliable operation of high density DRAM

Two design techniques are presented to improve the yield of high density DRAM product. One is bit line coupling (BLC) scheme and the other is electrical fuse (E-Fuse) circuit for reliable field programmable repair scheme. We obtain an improvement of 100 ms for the data retention time (tREF) using th...

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Bibliographic Details
Published in2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185) pp. 33 - 34
Main Authors Kyunam Lim, Sangseok Kang, Jonghyun Choi, Jaehoon Joo, Younsang Lee, Jinseok Lee, Sooin Cho, Byungil Ryu
Format Conference Proceeding
LanguageEnglish
Published IEEE 2001
Subjects
Boosting
Capacitance
Capacitors
Content addressable storage
Coupling circuits
Fuses
Latches
Product design
Random access memory
Voltage
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Summary:Two design techniques are presented to improve the yield of high density DRAM product. One is bit line coupling (BLC) scheme and the other is electrical fuse (E-Fuse) circuit for reliable field programmable repair scheme. We obtain an improvement of 100 ms for the data retention time (tREF) using the BLC scheme. BLC scheme also improves the low VCC margin by 0.3 V and the RAS to CAS delay time (tRCD) by 1.5 ns. Differential current evaluation for the E-fuse implementation shows polysilicon fuse fail rate <10/sup -12/.
ISBN:9784891140144
4891140143
DOI:10.1109/VLSIC.2001.934186