A decompression architecture for low power embedded systems

We present an architecture for embedded systems that decompresses offline-compressed instructions during runtime. This is useful for compressed code systems where instructions are stored in a compressed format and decompressed on demand. The result is a significant reduction in power consumption, an...

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Bibliographic Details
Published inProceedings 2000 International Conference on Computer Design pp. 571 - 574
Main Authors Lekatsas, H., Henkel, J., Wolf, W.
Format Conference Proceeding
LanguageEnglish
Published IEEE 2000
Subjects
Automata
Bandwidth
Decoding
Embedded system
Energy consumption
Engines
National electric code
Process design
Runtime
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Summary:We present an architecture for embedded systems that decompresses offline-compressed instructions during runtime. This is useful for compressed code systems where instructions are stored in a compressed format and decompressed on demand. The result is a significant reduction in power consumption, and in most cases a performance improvement. The stand-alone decompression engine is placed between the instruction cache and the CPU (post-cache architecture) as we have found this to be the most power-efficient architecture. This paper describes the design of this unit in detail and analyzes its power consumption and performance.
ISBN:9780769508016
0769508014
ISSN:1063-6404
2576-6996
DOI:10.1109/ICCD.2000.878345