Design and performance evaluation of an adaptive cache coherence protocol

In shared-memory multiprocessor systems, the local caches which are used to tolerate the performance gap between processor and memory cause additional bus transactions to maintain the coherency of shared data. Especially, coherency misses and data traffic due to spatial locality and false sharing ha...

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Bibliographic Details
Published inProceedings 1998 International Conference on Parallel and Distributed Systems (Cat. No.98TB100250) pp. 33 - 40
Main Authors Won-Kee Hong, Nam-Hee Kim, Shin-Dug Kim
Format Conference Proceeding
LanguageEnglish
Published IEEE 1998
Subjects
Access protocols
Computer science
Degradation
Delay
Electrical capacitance tomography
Parallel processing
System performance
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Summary:In shared-memory multiprocessor systems, the local caches which are used to tolerate the performance gap between processor and memory cause additional bus transactions to maintain the coherency of shared data. Especially, coherency misses and data traffic due to spatial locality and false sharing have a significant effect on the system performance. In this approach, an adaptive cache coherence protocol based on the sectored cache is introduced. It determines the size of a block to be migrated or invalidated dynamically, depending on the transfer mode, so that it can exploit the spatial locality and reduce useless data traffic due to false sharing at the same time. This protocol is evaluated via event-driven simulation, and its results show a 58% decrease in the data traffic and a 45% decrease in the cache miss ratio. Thus, the adaptive cache coherence protocol provides about a 56% improvement in the execution time.
ISBN:0818686030
9780818686030
ISSN:1521-9097
2690-5965
DOI:10.1109/ICPADS.1998.741017