Power constrained design of multiprocessor interconnection networks

• Published in: Proceedings International Conference on Computer Design VLSI in Computers and Processors pp. 408 - 416
• Main Authors: Patel, C.S., Chai, S.M., Yalamanchili, S., Schimmel, D.E.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 1997
• Subjects: Computer architecture; Computer networks; Delay effects; Multiprocessor interconnection networks; Personal digital assistants; Portable computers; Power dissipation; Power system modeling; Routing; Switches
• ISBN: 9780818682063; 081868206X
• ISSN: 1063-6404
• DOI: 10.1109/ICCD.1997.628902

The paper considers the power constrained design of orthogonal multiprocessor interconnection networks. The authors present a detailed model of message latency as a function of topology, technology architecture, and power. This model is then used to analyze a number of interesting scenarios, providing a sound engineering basis for interconnection network design in these cases. For example, they have observed that under a fixed power constraint, the network dimension which achieves minimal latency is a slowly growing function of system size. In addition, as they increase the available power per node for a fixed system size, the dimension at which message latency is minimized shifts towards higher dimensional networks.