A massively parallel multithreaded architecture: DAVRID

MPAs (massively parallel architectures) should address two fundamental issues for scalability: synchronization and communication latency. Dataflow architectures cause problems of excessive synchronization costs and inefficient execution of sequential programs while they offer the ability to exploit...

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Bibliographic Details
Published inProceedings 1994 IEEE International Conference on Computer Design: VLSI in Computers and Processors pp. 70 - 74
Main Authors Sangho Ha, Junghwan Kim, Eunha Rho, Yoonhee Nah, Sangyong Han, Daejoon Hwang, Heunghwan Kim, Seungho Cho
Format Conference Proceeding
LanguageEnglish
Published IEEE Comput. Soc. Press 1994
Subjects
Computer architecture
Computer science
Contracts
Costs
Data engineering
Delay
Processor scheduling
Registers
Scalability
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Summary:MPAs (massively parallel architectures) should address two fundamental issues for scalability: synchronization and communication latency. Dataflow architectures cause problems of excessive synchronization costs and inefficient execution of sequential programs while they offer the ability to exploit massive parallelism inherent in programs. In contrast, MPAs based on the von Neumann computational model may suffer from inefficient synchronization mechanism and communication latencies. DAVRID (Dataflow von Neumann, RISC Hybrid) is a massively parallel multithreaded architecture. By combining the advantages of the von Neumann model and the dataflow model, DAVRID preserves good single thread performance and tolerates latency and synchronization costs. We describe the DAVRID architecture and evaluate it through simulation results over several benchmarks.< >
ISBN:9780818665653
0818665653
DOI:10.1109/ICCD.1994.331857