The comparison of delay modeling for basic interconnect net topologies

This paper makes an attempt to compare several methods of interconnect delay modelling. The results of different interconnect delay analyses are given and compared with SPICE simulation results for testing basic interconnect net topology.

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Bibliographic Details
Published in1998 5th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.98EX105) pp. 468 - 471
Main Authors Sun Lingling, Yan Xiaolang, Wang Junhu, Cai Miaohua
Format Conference Proceeding
LanguageEnglish
Published IEEE 1998
Subjects
Circuit simulation
Circuit topology
Delay effects
Delay estimation
Integrated circuit interconnections
RLC circuits
Routing
SPICE
Testing
Very large scale integration
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Summary:This paper makes an attempt to compare several methods of interconnect delay modelling. The results of different interconnect delay analyses are given and compared with SPICE simulation results for testing basic interconnect net topology.
ISBN:0780343069
9780780343061
DOI:10.1109/ICSICT.1998.785923