Estimating the effect of contamination-induced leakage current in view of DRAM architectural trends

• Published in: Proceedings of 1994 IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop (ASMC) pp. 241 - 250
• Main Authors: Schmid, J.R., Parks, H.G., Craigin, R., Schrimpf, R.D.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 1994
• Subjects: Chemical processes; Contamination; Impurities; Leakage current; Life estimation; Lifetime estimation; Memory architecture; Predictive models; Random access memory; Upper bound
• ISBN: 0780320530; 9780780320536
• DOI: 10.1109/ASMC.1994.588261

Due to new memory-cell architectures, the leakage-current requirements for semiconductor memories will become less stringent with increased levels of integration. The implication of these requirements with regard to allowable metallic contamination levels is investigated with a one-dimensional model based on Shockley-Read-Hall generation-recombination. The model was developed to predict leakage-current in carrier-depleted regions as a function of basic process and metallic contaminant parameters. As device dimensions are reduced, transition metal homogeneous contamination in process chemicals can be an important source of generation-recombination centers that result in the dominant generation-current in the space-charge region. The model allows an estimation of an upper bound for transition metal contamination in advanced processes and is applied for DRAM leakage predictions. Using the model, it is demonstrated that the trend toward lower leakage-current density requirements reverses after the 64-Mbit generation DRAM as a result of memory-cell architecture trends which significantly reduce the space-charge volume.