Accurate timing model for the CMOS inverter

This paper introduces an accurate, analytical timing model for the CMOS inverter. Analytical output waveform expressions for all the inverter operation regions and input waveform slopes are derived, which take into account the complete expression of the short-circuit current and the gate-to-drain co...

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Bibliographic Details
Published inProceedings of Third International Conference on Electronics, Circuits, and Systems Vol. 1; pp. 89 - 92 vol.1
Main Authors Bisdounis, L., Nikolaidis, S., Koufopavlou, O., Goutis, C.
Format Conference Proceeding
LanguageEnglish
Published IEEE 1996
Subjects
Capacitance
Coupling circuits
Differential equations
Inverters
MOS devices
Physics computing
Propagation delay
Semiconductor device modeling
Threshold voltage
Timing
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Summary:This paper introduces an accurate, analytical timing model for the CMOS inverter. Analytical output waveform expressions for all the inverter operation regions and input waveform slopes are derived, which take into account the complete expression of the short-circuit current and the gate-to-drain coupling capacitance.
ISBN:9780780336506
078033650X
DOI:10.1109/ICECS.1996.582696