An x86 load/store unit with aggressive scheduling of load/store operations

Because of register-memory instruction set architecture and limited register set, there are significant amounts of memory access instructions in x86 microprocessors. As the higher issue degree of superscalar microprocessor is provided, an aggressive scheduling policy of load/store operations becomes...

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Bibliographic Details
Published inProceedings 1998 International Conference on Parallel and Distributed Systems (Cat. No.98TB100250) pp. 496 - 503
Main Authors Hui-Yue Hwang, R-Ming Shiu, Jyh-Jiun Shann
Format Conference Proceeding
LanguageEnglish
Published IEEE 1998
Subjects
Analytical models
Contracts
Electrical capacitance tomography
Job shop scheduling
Memory architecture
Microprocessors
Postal services
Processor scheduling
Registers
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Summary:Because of register-memory instruction set architecture and limited register set, there are significant amounts of memory access instructions in x86 microprocessors. As the higher issue degree of superscalar microprocessor is provided, an aggressive scheduling policy of load/store operations becomes crucial. We examine the scheduling policies of loads/stores on x86 superscalar microprocessors and propose a new aggressive scheduling policy called load speculation, which allows loads to precede the previous unsolved pending stores. Simulation results show that the load speculation achieves the higher performance in comparison with the traditional scheduling policies such as load bypassing and load forwarding. Furthermore, by reducing the pipeline stages, the load speculation can achieve even higher performance.
ISBN:0818686030
9780818686030
ISSN:1521-9097
2690-5965
DOI:10.1109/ICPADS.1998.741123