Self-testable pipelined ADC with low hardware overhead

This paper presents a BIST scheme for the structural testing of pipelined ADCs. The operational principle relies on testing every ADC stage reconfigured as an A/D-D/A block and applying as input a set of analog DC values. These values have been determined as the appropriate and simple stimuli giving...

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Bibliographic Details
Published inProceedings 19th IEEE VLSI Test Symposium. VTS 2001 pp. 272 - 277
Main Authors Peralias, E.J., Huertas, G., Rueda, A., Huertas, J.L.
Format Conference Proceeding
LanguageEnglish
Published IEEE 2001
Subjects
Built-in self-test
Consumer electronics
Costs
Hardware
Maintenance
Manufacturing industries
Microelectronics
Production
Test equipment
Testing
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Summary:This paper presents a BIST scheme for the structural testing of pipelined ADCs. The operational principle relies on testing every ADC stage reconfigured as an A/D-D/A block and applying as input a set of analog DC values. These values have been determined as the appropriate and simple stimuli giving a single output signature. A new output signature is proposed allowing a low-cost digital domain test evaluation. The new technique is intended to be used in pipelined converters of an arbitrary number of conversion stages and provided with a digital correction mechanism.
ISBN:9780769511221
0769511228
DOI:10.1109/VTS.2001.923450