Register renaming for x86 superscalar design

Register renaming eliminates storage conflicts for registers to allow more instruction level parallelism. This idea requires nontrivial implementation, however, especially when registers are accessible with different fields and data lengths. As a result, not all bits in a register are to be updated...

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Bibliographic Details
Published inProceedings of 1996 International Conference on Parallel and Distributed Systems pp. 336 - 343
Main Authors Chang-Chung Liu, R-Ming Shiu, Chung-Ping Chung
Format Conference Proceeding
LanguageEnglish
Published IEEE 1996
Subjects
Computational modeling
Computer science
Costs
Councils
Electrostatic precipitators
Hardware
Microprocessors
Out of order
Parallel processing
Registers
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Summary:Register renaming eliminates storage conflicts for registers to allow more instruction level parallelism. This idea requires nontrivial implementation, however, especially when registers are accessible with different fields and data lengths. As a result, not all bits in a register are to be updated upon a register write, and a register read may be data-dependent on multiple register writes. We propose two hardware renaming schemes to solve these difficulties: One for its ultimate performance, and the other for its desirable cost/performance ratio. We evaluate these two schemes on an aggressive superscalar machine model for Intel 80/spl times/86 architecture. Simulation results show that the second scheme can effectively reduce the hardware cost while retaining about 99% of the performance of the first.
ISBN:9780818672675
0818672676
DOI:10.1109/ICPADS.1996.517580