Performance modeling for system design: an MPEG A/V decoder example

This paper describes a system level performance simulation methodology for VLSI system design of complex signal processing devices. This methodology also provides a means for HW/SW co-simulation and co-design. An MPEG audio/video decoder example illustrates this approach. Through this example we dem...

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Bibliographic Details
Published in1998 IEEE International Symposium on Circuits and Systems (ISCAS) Vol. 6; pp. 203 - 206 vol.6
Main Authors Hocevar, D.E., Sriram, S., Ching-Yu Hung
Format Conference Proceeding
LanguageEnglish
Published IEEE 1998
Subjects
Computational modeling
Decoding
Hardware
Process design
Software libraries
Synchronization
Testing
Transform coding
Very large scale integration
Video signal processing
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Summary:This paper describes a system level performance simulation methodology for VLSI system design of complex signal processing devices. This methodology also provides a means for HW/SW co-simulation and co-design. An MPEG audio/video decoder example illustrates this approach. Through this example we demonstrate an extremely fast simulation method that can process multiple frames of MPEG-2 compressed video per minute, and provides the necessary information for developing and evaluating the decoder architecture. This also allows for rapid simulation over numerous test bitstreams. Our methodology allows us to measure many different performance metrics, quickly construct and alter the simulation model, process actual bitstreams, and generate test cases. A pathway for developing detailed simulation models of the lower levels of the design process is also discussed.
ISBN:9780780344556
0780344553
DOI:10.1109/ISCAS.1998.705247