Low-power multipliers by minimizing inter-data switching activities

By using the radix-4 Booth algorithm, low-power 2's complement multipliers are developed by minimizing inter-data switching activities. Before performing multiplication, one of two input data with a smaller dynamic range is partitioned into Booth codes, thereby increasing probabilities of parti...

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Bibliographic Details
Published inProceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144) Vol. 1; pp. 88 - 92 vol.1
Main Authors Sandy Wang, Yi-Wen Wu, Chen, O.T.-C., Ruey-Liang Ma
Format Conference Proceeding
LanguageEnglish
Published IEEE 2000
Subjects
Arithmetic
Circuits and systems
Decoding
Dynamic range
Laboratories
Microelectronics
Partitioning algorithms
Power dissipation
Power system reliability
Switching circuits
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Summary:By using the radix-4 Booth algorithm, low-power 2's complement multipliers are developed by minimizing inter-data switching activities. Before performing multiplication, one of two input data with a smaller dynamic range is partitioned into Booth codes, thereby increasing probabilities of partial products being zero. In addition, functional blocks for adding zero preserve their previous input states. As compared to the conventional Wallace-tree multiplier, the two 16/spl times/16-bit multipliers proposed herein are demonstrated to have lower power dissipation.
ISBN:9780780364752
0780364759
DOI:10.1109/MWSCAS.2000.951593