IBM single chip RISC processor (RSC)

A highly integrated single-chip microprocessor is described that combines a powerful RISC architecture and superscalar machine organization with system design optimizations appropriate for low cost workstation applications. This RISC single-chip (RSC) processor can dispatch up to two instructions pe...

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Bibliographic Details
Published inProceedings 1992 IEEE International Conference on Computer Design: VLSI in Computers & Processors pp. 200 - 204
Main Authors Moore, C.R., Balser, D.M., Muhich, J.S., East, R.E.
Format Conference Proceeding
LanguageEnglish
Published IEEE Comput. Soc. Press 1992
Subjects
Built-in self-test
Clocks
Cost function
Design optimization
Engineering management
Error correction codes
Memory management
Microprocessors
Reduced instruction set computing
Workstations
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Summary:A highly integrated single-chip microprocessor is described that combines a powerful RISC architecture and superscalar machine organization with system design optimizations appropriate for low cost workstation applications. This RISC single-chip (RSC) processor can dispatch up to two instructions per cycle and concurrently execute up to three instructions per cycle. The design integrates a fixed-point execution unit, a floating-point execution unit, an in-page branch unit, an 8-Kbyte unified cache, a memory management unit, a DMA controller, an interrupt controller, ECC on the memory interface, a real-time clock and decrementer, built-in self-test, and a versatile engineering support processor interface on a single die.< >
ISBN:9780818631108
0818631104
DOI:10.1109/ICCD.1992.276248