A novel logic compatible gain cell with two transistors and one capacitor

Summary form only given. In consumer electronics, cost-effective embedded technology is an important subject. We propose a novel, cost-effective gain cell for memory embedded in logic LSIs. The new cell consists of two conventional bulk transistors and one MOS capacitor. It can be fabricated using t...

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Bibliographic Details
Published in2000 Symposium on VLSI Technology pp. 168 - 169
Main Authors Ikeda, N., Terano, T., Moriya, H., Emori, T., Kobayashi, T.
Format Conference Proceeding
LanguageEnglish
Published IEEE 2000
Subjects
Capacitance
CMOS logic circuits
Costs
Fabrication
MOS capacitors
MOSFETs
Random access memory
Research and development
Threshold voltage
Ultra large scale integration
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Summary:Summary form only given. In consumer electronics, cost-effective embedded technology is an important subject. We propose a novel, cost-effective gain cell for memory embedded in logic LSIs. The new cell consists of two conventional bulk transistors and one MOS capacitor. It can be fabricated using the pure logic process with a few additional process steps. The fabrication cost of this cell is lower than that of DRAM or SRAM at a memory density in the 1/spl sim/100 Mbit range.
ISBN:0780363051
9780780363052
DOI:10.1109/VLSIT.2000.852812