Robustness of LDMOS power transistors in SOI-BCD processes and derivation of design rules using thermal simulation

• Published in: Proceedings of the 13th International Symposium on Power Semiconductor Devices & ICs. IPSD '01 (IEEE Cat. No.01CH37216) pp. 157 - 160
• Main Authors: Krabbenborg, B.H., Van der Pol, J.A.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 2001
• Subjects: Area measurement; Failure analysis; Impedance; Power measurement; Power transistors; Robustness; Semiconductor optical amplifiers; Temperature dependence; Temperature measurement; Temperature sensors
• ISBN: 9784886860569; 4886860567
• ISSN: 1063-6854; 1946-0201
• DOI: 10.1109/ISPSD.2001.934579

In SOI devices, the buried oxide alters the thermal impedance compared to a bulk device and a gives a higher temperature rise that influences the robustness of the device. In this paper, power LDMOS transistors (with integrated temperature sensors) in an SOI-process are evaluated with Safe Operating Area (SOA) measurements. The failure mechanism based on triggering of the parasitic bipolar, is discussed with the aid of dynamic temperature measurements. The results show that the failure energy can be related to a critical temperature rise that depends on V/sub DS/. Consequently, the thermal impedance and V/sub DS/ fully determine the failure energy. Hence, 3D thermal simulation can be used as a tool for dimensioning power transistors. A comparison of SOI-DMOS with bulk-DMOS and bulk-Bipolar shows that in SOI it is still very well possible to create power devices with a good SOA.