Pipelined FIR filter architecture and increasing performance of decision-feedback equalizer

In this paper, we first present a procedure to efficiently use Booth-encoding-based input decomposition scheme for FIR filter implementations. We also show that the high-order/high-speed FIR filter architectures usually have unavoidable pipelining delays, and that they add to the feedback loop delay...

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Bibliographic Details
Published in1996 IEEE International Symposium on Circuits and Systems (ISCAS) Vol. 2; pp. 564 - 567 vol.2
Main Author Il-Taek Lim
Format Conference Proceeding
LanguageEnglish
Published IEEE 1996
Subjects
Added delay
Broadcasting
Clocks
Decision feedback equalizers
Degradation
Feedback loop
Finite impulse response filter
Hardware
Intersymbol interference
Pipeline processing
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Summary:In this paper, we first present a procedure to efficiently use Booth-encoding-based input decomposition scheme for FIR filter implementations. We also show that the high-order/high-speed FIR filter architectures usually have unavoidable pipelining delays, and that they add to the feedback loop delay of the decision-feedback equalizers. The added delay degrades the performance of the equalizer for strong near-ISI signals. Finally, we present a new decision-feedback equalizer architecture which functions perfectly even though strong near-ISI signals exist in the channel.
ISBN:9780780330733
0780330730
DOI:10.1109/ISCAS.1996.541787