Mismatch characterization of small size MOS transistors

A test chip for characterization of transistor mismatch in a standard 1.2 /spl mu/m CMOS technology is presented. A new algorithm for matching parameter extraction has been used. Mismatch parameters based on measurements on 12000 nMOS and 10000 pMOS transistors have been extracted. It is observed th...

Full description

Saved in:
Bibliographic Details
Published inProceedings International Conference on Microelectronic Test Structures pp. 271 - 276
Main Authors Bastos, J., Steyaert, M., Roovers, R., Kinget, P., Sansen, W., Graindourze, B., Pergoot, A., Janssens, E.
Format Conference Proceeding
LanguageEnglish
Published IEEE 1995
Subjects
CMOS technology
Erbium
MOS devices
MOSFETs
Packaging
Parameter extraction
Semiconductor device measurement
Size measurement
Testing
Threshold voltage
Online AccessGet full text

Cover

More Information
Summary:A test chip for characterization of transistor mismatch in a standard 1.2 /spl mu/m CMOS technology is presented. A new algorithm for matching parameter extraction has been used. Mismatch parameters based on measurements on 12000 nMOS and 10000 pMOS transistors have been extracted. It is observed that the threshold voltage mismatch linear dependency on the inverse of the square root of the effective channel area no longer holds for transistors of 1.2 /spl mu/m channel length. An extended model based on the physical causes of threshold voltage mismatch is proposed.
ISBN:9780780320659
0780320654
DOI:10.1109/ICMTS.1995.513986