Optimal clock period clustering for sequential circuits with retiming

• Published in: Proceedings International Conference on Computer Design VLSI in Computers and Processors pp. 122 - 127
• Main Authors: Karandikar, A.K., Peichen Pan, Liu, C.L.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 1997
• Subjects: Clocks; Clustering algorithms; Combinational circuits; Delay; Design automation; Flip-flops; Heuristic algorithms; Partitioning algorithms; Sequential circuits; Very large scale integration
• ISBN: 9780818682063; 081868206X
• ISSN: 1063-6404
• DOI: 10.1109/ICCD.1997.628858

We consider the problem of clustering sequential circuits subject to a bound on the area of each cluster, with the objective of minimizing clock period. Current algorithms address combinational circuits only, and treat a sequential circuit as a special case, by removing the flip-flops (FFs) and clustering the remaining combinational logic. This approach segments a circuit and assumes the positions of the FFs are fixed. The positions of FFs are in fact dynamic, because of retiming. As a result, current algorithms can only consider a small portion of the available solution space. In this paper, we present a clustering algorithm that does not remove the FFs. It also considers the effect of retiming. The algorithm can produce clustering solutions with optimal clock periods under the unit delay model. For the general delay model, it can produce clustering solutions with clock periods provably close to minimum.