A test generation system for path delay faults

A complete test pattern generation system for path delay faults is presented. The test pattern generator is based on PODEM using a 5-valued logic. Techniques to prune the search space for test pattern generation are proposed. Since the number of paths for test generation can be exponential in the nu...

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Bibliographic Details
Published inProceedings 1989 IEEE International Conference on Computer Design: VLSI in Computers and Processors pp. 40 - 43
Main Authors Patil, S., Reddy, S.M.
Format Conference Proceeding
LanguageEnglish
Published IEEE Comput. Soc. Press 1989
Subjects
Circuit faults
Circuit testing
Clocks
Delay systems
Logic circuits
Logic testing
Propagation delay
Sequential circuits
System testing
Test pattern generators
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Summary:A complete test pattern generation system for path delay faults is presented. The test pattern generator is based on PODEM using a 5-valued logic. Techniques to prune the search space for test pattern generation are proposed. Since the number of paths for test generation can be exponential in the number of lines in the network, criteria and efficient algorithms to prune the number of paths for test generation are presented. The test generation system is evaluated using the ISCAS combinational benchmark circuits.< >
ISBN:9780818619717
0818619716
DOI:10.1109/ICCD.1989.63324