IBM second-generation RISC machine organization

• Published in: Proceedings 1989 IEEE International Conference on Computer Design: VLSI in Computers and Processors pp. 138 - 142
• Main Authors: Bakoglu, H.B., Grohoski, G.F., Thatcher, L.E., Kahle, J.A., Moore, C.R., Tuttle, D.P., Maule, W.E., Hardell, W.R., Hicks, D.A., Nguyenphu, M., Montoye, R.K., Glover, W.T., Dhawan, S.
• Format: Conference Proceeding
• Language: English
• Published: IEEE Comput. Soc. Press 1989
• Subjects: Bandwidth; Computer architecture; Concurrent computing; Delay; Engines; Hardware; Process design; Reduced instruction set computing; Registers; Workstations
• ISBN: 9780818619717; 0818619716
• DOI: 10.1109/ICCD.1989.63344

A highly concurrent second-generation RISC (reduced-instruction-set computer) that combines a powerful RISC architecture with sophisticated hardware design techniques to achieve a short cycle time and a low cycles-per-instruction (CPI) ratio is described. Like earlier RISC processors, this design uses a register-oriented instruction set, the CPU is hardwired rather than microcoded, and it features a pipelined implementation. Unlike earlier RISC processors, however, several advanced architectural and implementation features are used, including separate instruction and data caches, zero-cycle branches, multiple-instruction dispatch, and simultaneous execution of fixed- and floating-point instructions. The CPU has a four-word data bus to main memory, a four-word instruction-fetch bus from the I-cache arrays, and a two-word data bus between the D-cache and floating-point unit. The CPU has a full 64-b floating-point engine, and thirty-two 64-b floating point registers in addition to thirty-two 32-b fixed-point registers. In a single cycle, four instructions can be executed simultaneously.< >