Asynchronous PRAMs are (almost) as good as synchronous PRAMs

A PRAM (parallel random-access-machine) model that allows processors to have arbitrary asynchronous behavior is introduced. The main result shows that any n-processor CRCW (concurrent-read, concurrent-write) PRAM program can be simulated on an asynchronous CRCW PRAM using O(n) expected work per para...

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Bibliographic Details
Published inFoundations of Computer Science, 31st Symposium pp. 590 - 599 vol.2
Main Authors Martel, C., Subramonian, R., Part, A.
Format Conference Proceeding
LanguageEnglish
Published IEEE Comput. Soc. Press 1990
Subjects
Algorithm design and analysis
Analytical models
Computational modeling
Computer architecture
Computer science
Concurrent computing
Error correction
Failure analysis
Large-scale systems
Phase change random access memory
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ISBN081862082X
9780818620829
DOI10.1109/FSCS.1990.89580

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Summary:A PRAM (parallel random-access-machine) model that allows processors to have arbitrary asynchronous behavior is introduced. The main result shows that any n-processor CRCW (concurrent-read, concurrent-write) PRAM program can be simulated on an asynchronous CRCW PRAM using O(n) expected work per parallel step and up to n/log n log*n asynchronous processors. It is shown that a synchronization primitive for n parallel instructions can be computed using O(n) expected work by a system of asynchronous processors. Since a special case of asynchronous behavior is a fail-stop error, the simulation technique described above can convert any PRAM program into a PRAM program that is resistant to all fail-stop errors and has the same expected work as the original program.< >
ISBN:081862082X
9780818620829
DOI:10.1109/FSCS.1990.89580