Backside Thinning Process Development for High-Density TSV in a 3-Layer Integration

This paper describes recent developments in the field of high density Through Silicon Vias (TSV) with a focus on the backside thinning flow (grinding, CMP, metrology) for TSV depths of 6μm or lower. Stringent process control was implemented from grinding to CMP finishing steps to obtain remarkably l...

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Bibliographic Details
Published in2024 IEEE 74th Electronic Components and Technology Conference (ECTC) pp. 370 - 377
Main Authors Bouis, Renan, Marchand, Jeremy, Andre, Agathe, Borel, Stephan, Dechamp, Jerome, Vignoud, Lionel, Valentin, Paul, Assous, Myriam, Hebras, Damien
Format Conference Proceeding
LanguageEnglish
Published IEEE 28.05.2024
Subjects
3D integration
backside thinning
CMP
Electronic components
ellipsometry
grinding
interferometry
Metrology
Process control
Reproducibility of results
Silicon
stacking
Three-dimensional displays
Through-silicon vias
TTV
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Summary:This paper describes recent developments in the field of high density Through Silicon Vias (TSV) with a focus on the backside thinning flow (grinding, CMP, metrology) for TSV depths of 6μm or lower. Stringent process control was implemented from grinding to CMP finishing steps to obtain remarkably low silicon Total Thickness Variations below 1μm.
ISSN:2377-5726
DOI:10.1109/ECTC51529.2024.00067