FPGA Implementation of a Wideband Multi-Gb/s 5G BF-OFDM Transceiver

This paper describes a Field Programmable Gate Array (FPGA) implementation of a multi-Gb/s Block Filtered (BF) OFDM transceiver, fully 5G NR compatible. The main obstacles for such a work are (i) the support of multiple configurations and parameters, (ii) the high bandwidth w.r.t the board clock fre...

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Bibliographic Details
Published in2021 Joint European Conference on Networks and Communications & 6G Summit (EuCNC/6G Summit) pp. 502 - 507
Main Authors Dore, Jean-Baptiste, Laugeois, Marc, Cassiau, Nicolas, Popon, Xavier
Format Conference Proceeding
LanguageEnglish
Published IEEE 08.06.2021
Subjects
5G mobile communication
BF-OFDM
Complexity theory
Filter banks
FPGA
Hardware
OFDM
parallelization
Transceivers
Transmitters
wideband
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Summary:This paper describes a Field Programmable Gate Array (FPGA) implementation of a multi-Gb/s Block Filtered (BF) OFDM transceiver, fully 5G NR compatible. The main obstacles for such a work are (i) the support of multiple configurations and parameters, (ii) the high bandwidth w.r.t the board clock frequency and (iii) the intrinsic complexity of BF-OFDM. We prove that despite these barriers an hardware implementation of this waveform is possible, even with a bandwidth up to 400 MHz. We based our developments on the following pillars: smart layout of the basic modules, parallelization of dedicated functions design and ad hoc architecture. Measurements and complexity analysis demonstrate the high flexibility of BF-OFDM.
ISSN:2575-4912
DOI:10.1109/EuCNC/6GSummit51104.2021.9482424