FPGA prototyping of large reconfigurable ADPLL network for distributed clock generation

• Published in: 2013 International Conference on Reconfigurable Computing and FPGAs (ReConFig) pp. 1 - 6
• Main Authors: Chuan Shan, Zianbetov, Eldar, Weiqiang Yu, Anceau, Francois, Billoint, Olivier, Galayko, Dimitri
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.12.2013
• Subjects: ADPLL; Application specific integrated circuits; Clocks; Field programmable gate arrays; FPGA; Oscillators; Phase frequency detector; Programming; prototyping; reconfigurability; Synchronization
• ISSN: 2325-6532; 2640-0472
• DOI: 10.1109/ReConFig.2013.6732295

In this paper, we present an FPGA modelling of a distributed and synchronized clock generation for different clock domains based on coupled all-digital phase locked loops (ADPLLs). An implementation of a programmable and reconfigurable 10 ×10 ADPLL network is described, designed for prototyping distributed clock generation in large synchronous system on chip (SoC). The paper emphasizes the reconfigurability of proposed system, which allows exploiting stability issues and nonlinear behavior of a N × M network of coupled oscillators (the dimension can be configured from 1 × 1 to 10 × 10). Configurations with different parameters are compared and analyzed. A dynamic setup mechanism is proposed, allowing selecting the desired synchronized state. Experimental results validate theoretical analysis about circuit parameters and demonstrate the global synchronization of network and performance for different configurations.