A study of predictable execution models implementation for industrial data-flow applications on a multi-core platform with shared banked memory

We study the implementation of data-flow applications on multi-core processor with on-chip shared multi-banked memory. Specifically, we consider the Kalray MPPA2 processor and three applications coded using the industrial toolchain SCADE Suite. We focus on the runtime environment assuming global sta...

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Bibliographic Details
Published in2020 IEEE Real-Time Systems Symposium (RTSS) pp. 283 - 295
Main Authors Schuh, Matheus, Maiza, Claire, Goossens, Joel, Raymond, Pascal, de Dinechin, Benoit Dupont
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.12.2020
Subjects
Data flow
Multi banked memory
Multi core
Multicore processing
Predictable Execution Models
Predictive models
Processor scheduling
Real-time systems
Runtime environment
SCADE
System-on-chip
Task analysis
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Summary:We study the implementation of data-flow applications on multi-core processor with on-chip shared multi-banked memory. Specifically, we consider the Kalray MPPA2 processor and three applications coded using the industrial toolchain SCADE Suite. We focus on the runtime environment assuming global static scheduling, time-triggered and non-preemptive execution of tasks. Our contributions include (i) a technique to implement SCADE applications compliant with execution models inspired by PREMs (PRe-dictable Execution Models), (ii) an exhaustive comparison of three execution models with and without isolation, and finally (iii) guidelines for predictable implementation of a data-flow application on multi-core processors with shared on-chip memory.
ISSN:2576-3172
DOI:10.1109/RTSS49844.2020.00034