Hardware architectures for successive cancellation decoding of polar codes

The recently-discovered polar codes are widely seen as a major breakthrough in coding theory. These codes achieve the capacity of many important channels under successive cancellation decoding. Motivated by the rapid progress in the theory of polar codes, we pro pose a family of architectures for ef...

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Bibliographic Details
Published in2011 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP) pp. 1665 - 1668
Main Authors Leroux, Camille, Tal, Ido, Vardy, Alexander, Gross, Warren J.
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.05.2011
Subjects
Complexity theory
Computer architecture
Decoding
Hardware
hardware implementation
Polar codes
Processor scheduling
Registers
successive cancellation decoding
Throughput
VLSI
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Summary:The recently-discovered polar codes are widely seen as a major breakthrough in coding theory. These codes achieve the capacity of many important channels under successive cancellation decoding. Motivated by the rapid progress in the theory of polar codes, we pro pose a family of architectures for efficient hardware implementation of successive cancellation decoders. We show that such decoders can be implemented with O(n) processing elements and O(n) memory elements, while providing constant throughput. We also pro pose a technique for overlapping the decoding of several consecutive codewords, thereby achieving a significant speed-up factor. We furthermore show that successive cancellation decoding can be implemented in the logarithmic domain, thereby eliminating the multiplication and division operations and greatly reducing the complexity of each processing element.
ISBN:9781457705380
1457705389
ISSN:1520-6149
DOI:10.1109/ICASSP.2011.5946819