Towards Gb/s turbo decoding of product code onto an FPGA device

• Published in: 2007 IEEE International Symposium on Circuits and Systems (ISCAS) pp. 909 - 912
• Main Authors: Leroux, Camille, Jego, Christophe, Adde, Patrick, Jezequel, Michel
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.05.2007
• Subjects: Bit error rate; Block codes; Field programmable gate arrays; Forward error correction; High speed optical techniques; Iterative decoding; Performance analysis; Product codes; Quality of service; Turbo codes

This paper presents the implementation, on an FPGA device of an ultra high rate block turbo code decoder. First, a complexity analysis of the elementary decoder leads to a low complexity decoder architecture (area divided by 2) for a negligible performance degradation. The resulting turbo decoder is...