Towards Gb/s turbo decoding of product code onto an FPGA device

• Published in: 2007 IEEE International Symposium on Circuits and Systems (ISCAS) pp. 909 - 912
• Main Authors: Leroux, Camille, Jego, Christophe, Adde, Patrick, Jezequel, Michel
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.05.2007
• Subjects: Bit error rate; Block codes; Field programmable gate arrays; Forward error correction; High speed optical techniques; Iterative decoding; Performance analysis; Product codes; Quality of service; Turbo codes
• ISBN: 1424409209; 9781424409204
• ISSN: 0271-4302; 2158-1525
• DOI: 10.1109/ISCAS.2007.378073

This paper presents the implementation, on an FPGA device of an ultra high rate block turbo code decoder. First, a complexity analysis of the elementary decoder leads to a low complexity decoder architecture (area divided by 2) for a negligible performance degradation. The resulting turbo decoder is implemented on a Xilinx Virtex II-Pro FPGA in a communication experimental setup. Based on an innovative architecture which enables the memory blocks between all half-iterations to be removed and clocked at only 37.5 MHz, the turbo decoder processes input data at 600Mb/s. The component code is an extended Bose, Ray-Chaudhuri, Hocquenghem (eBCH(16,11)) code. Ultra high-speed block turbo decoder architectures meet the demand for even higher data rates and open up new opportunities for the next generations of communication systems such as fiber optic transmissions.