Data retention fault in SRAM memories: analysis and detection procedures

• Published in: 23rd IEEE VLSI Test Symposium (VTS'05) pp. 183 - 188
• Main Authors: Dilillo, L., Girard, P., Pravossoudovitch, S., Virazel, A., Hage-Hassan, M.B.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 2005; IEEE Computer Society
• Subjects: Circuit faults; Circuit testing; Electric resistance; Electrical fault detection; Engineering Sciences; Fault detection; Integrated circuit noise; Micro and nanotechnologies; Microelectronics; Random access memory; Robots; System-on-a-chip; Uniform resource locators
• ISBN: 0769523145; 9780769523149
• ISSN: 1093-0167; 2375-1053
• DOI: 10.1109/VTS.2005.37

In this paper, we present a novel study on data retention faults (DRFs) in SRAM memories. We analyze in detail the electrical origins of these faults, starting from the most common till those that lead to what we have called hard to detect DRFs. In general, DRFs are supposed to be produced by very high resistive-open defects that affect the refreshment loop of the core-cell. We demonstrate that lower values of resistance may produce hard to detect DRFs. Moreover, each resistive-open defect produces a particular faulty behavior of the core-cell that changes for different ranges of the resistive value. We analyze different cases and we propose for each one an efficient test procedure based on March tests. In particular, we propose to stimulate the defective cells in some cases by indirect accesses and in some other cases by emphasizing natural noise phenomenon of SRAM memories (such as the ground bounce).