Framework for high level estimations of signal processing VLSI implementations

• Published in: Journal of VLSI signal processing Vol. 25; no. 3; pp. 261 - 284
• Main Authors: Diguet, J Ph, Chillet, D, Sentieys, O
• Format: Journal Article
• Language: English
• Published: 01.07.2000
• ISSN: 0922-5773
• DOI: 10.1023/A:1008191708726

This paper deals with the presentation of a framework for the rapid prototyping of Digital Signal Processing applications. The BSS framework enables both synthesis of dedicated VLSI circuits and cost, performance estimation. The latter can be used at different accuracy levels and can help the designer in selecting a proper algorithm in order to improve the global performance of its implementation. The cost estimation takes into account both the processing unit, including operators, registers, interconnections, and memory units. The implemented estimation techniques are presented and include functional unit number bound calculation, probabilistic cost estimation of processing unit components, and memory unit area evaluation. We demonstrate, on a real application, that cost/signal processing quality trade-offs can be achieved while changing the type of algorithm and the number of filter taps for a given algorithm specification.