Architecture for Highly Reliable Embedded Flash Memories

• Published in: 2007 IEEE Design and Diagnostics of Electronic Circuits and Systems pp. 1 - 6
• Main Authors: Godard, B., Daga, J.-M., Torres, L., Sassatelli, G.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.04.2007
• Subjects: Computer architecture; Error correction; Error correction codes; Flash memory; Logic; Memory architecture; Nonvolatile memory; Redundancy; System-on-a-chip; Threshold voltage
• ISBN: 9781424411610; 1424411610
• DOI: 10.1109/DDECS.2007.4295257

Non-volatile embedded Flash (eFlash) memories are very popular in Systems-on-a-Chip (SoC). These memories are based on the well-known floating gate concept. While densities and quality constraints are increasing, the reliability becomes a growing up issue. For eFlash memories, endurance and retention issues are at the root of reliability losses. To improve reliability, eFlash memories designs usually use techniques such as Error Correcting Codes (ECC), Redundancy and Threshold Voltage (V T ) Analysis. In this paper, an implementation of these techniques is proposed through an architecture. Thanks to eFlash specificity, the correction capacity is improved via a double correction scheme. Additionally, each time an operation is performed on a memory element, a smart reliability management tracks online errors and weak bits. When few issues in a word catch out the double error correction scheme, a refresh and repair with low redundancy process is engaged.