Etching process scalability and challenges for ULK materials

• Published in: 2010 IEEE International Interconnect Technology Conference pp. 1 - 3
• Main Authors: Chevolleau, T, Posseme, N, David, T, Bouyssou, R, Ducote, J, Bailly, F, Darnon, M, El Kodadi, M, Besacier, M, Licitra, C, Guillermet, M, Ostrovsky, A, Verove, C, Joubert, O
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.06.2010
• Subjects: Dielectrics; Etching; Integrated circuit interconnections; Integrated circuit technology; Plasma applications; Plasma devices; Plasma materials processing; Plasma x-ray sources; Radar measurements; Scalability
• ISBN: 1424476763; 9781424476763
• ISSN: 2380-632X; 2380-6338
• DOI: 10.1109/IITC.2010.5510735

With the scaling down of integrated circuit devices, a constant effort is needed to improve the patterning technologies of interconnect stacks using either the metallic masking strategy or the organic masking strategy. Critical dimensions and profile control, plasma-induced damages (modifications, post etch residues, porous SiOCH roughening) are the key challenges to successfully pattern dual damascene porous SiOCH structures. We have compared the patterning performances of both masking strategies in terms of profile control. One of the main challenges is to optimize the plasma processes to minimize the dielectric sidewall modification. This has been achieved by using optimized or new characterization techniques such as scatterometric porosimetry, infrared spectroscopy, x-ray photoelectron spectroscopy.