A bi-objective heuristic for heterogeneous MPSoC design space exploration

Recent technology advances allow new generation reconfigurable-based embedded systems to contain a large number of cores and reconfigurable logic elements. Consequently, to take benefit of such very powerful hybrid reconfigurable MPSoC, designers need tools to explore the large design space of the p...

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Bibliographic Details
Published in2015 10th International Design & Test Symposium (IDT) pp. 90 - 95
Main Authors Mediouni, Braham Lotfi, Niar, Smail, Benmansour, Rachid, Benatchba, Karima, Koudil, Mouloud
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.12.2015
Subjects
Acceleration
Algorithm design and analysis
Computer architecture
Field programmable gate arrays
Genetic algorithms
Hardware
Space exploration
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Summary:Recent technology advances allow new generation reconfigurable-based embedded systems to contain a large number of cores and reconfigurable logic elements. Consequently, to take benefit of such very powerful hybrid reconfigurable MPSoC, designers need tools to explore the large design space of the possible configurations. In this paper, we develop a new hybrid bi-objective genetic and parallel variable neighborhood descent algorithm (GA-PVNS) to determine close to optimal configurations for heterogeneous FPGA-based MPSoC (Ht-MPSoC). Our exploration method aims to optimize simultaneously two objectives, namely area on the FPGA and execution time, taking advantage of the Genetic Algorithm (GA) diversification ability and the intensification provided by Variable Neighborhood Search (VNS) algorithm. Our design space includes Ht-MPSoC with private and shared HW accelerators on FPGA. Compared to exact methods, our algorithm determines very satisfactory multi-objective configurations in a very reduced execution time.
DOI:10.1109/IDT.2015.7396742