Flexible design methodology for spike encoding implementation on FPGA

Spiking Neural Networks (SNNs) are promising candidates for low power and low latency embedded artificial intelligence, e.g., for edge computing. There is, however, a lack of naturally event-based sensors that could directly feed those networks, except for a few specialized flagship examples like ne...

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Bibliographic Details
Published in2022 IEEE Biomedical Circuits and Systems Conference (BioCAS) pp. 379 - 383
Main Authors Gillet, Clemence, Vincent, Adrien F., Le Gal, Bertrand, Saighi, Sylvain
Format Conference Proceeding
LanguageEnglish
Published IEEE 13.10.2022
Subjects
Computer architecture
data encoding
Design methodology
edge computing
Encoding
Energy consumption
Hardware
high level synthesis
Software
Software algorithms
spike sorting
Spiking neural networks
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Summary:Spiking Neural Networks (SNNs) are promising candidates for low power and low latency embedded artificial intelligence, e.g., for edge computing. There is, however, a lack of naturally event-based sensors that could directly feed those networks, except for a few specialized flagship examples like neuromorphic retinas. Using conventional sensors in conjunction with SNNs requires to encode their outputs into spikes, which can be detrimental to energy consumption or latency when performed in software. Spike-encoding algorithms have been studied within specific contexts in the literature but are often limited to a software implementation. Here we introduce a flexible design methodology for implementing a generalized version of such a spike-encoder on Field Programmable Gate Array (FPGA). Our approach relies on High-Level Synthesis, which allows to quickly evaluate different hardware architectures to tailor the solution to the application needs. This work could accelerate the development of lower power and lower latency smart sensors by combining conventional, possibly off-the-shelf, sensors with hardware SNNs.
DOI:10.1109/BioCAS54905.2022.9948601