An ultra-low power iterative clique-based neural network integrated in 65-nm CMOS

Clique-based neural networks are less complex than commonly used neural network models. They have a limited connectivity and are composed of simple functions. They are thus adapted to implement neuro-inspired computation units operating under severe energy constraints. This paper shows an ST 65-nm C...

Full description

Saved in:
Bibliographic Details
Published in2017 15th IEEE International New Circuits and Systems Conference (NEWCAS) pp. 5 - 8
Main Authors Chollet, Paul, Larras, Benoit, Lahuec, Cyril, Seguin, Fabrice, Arzel, Matthieu
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.06.2017
Subjects
Biological neural networks
Current measurement
Energy consumption
Integrated circuit modeling
Iterative decoding
Neurons
Transistors
Online AccessGet full text

Cover

More Information
Summary:Clique-based neural networks are less complex than commonly used neural network models. They have a limited connectivity and are composed of simple functions. They are thus adapted to implement neuro-inspired computation units operating under severe energy constraints. This paper shows an ST 65-nm CMOS ASIC implementation for a 30-neuron clique-based neural network circuit. With a 1V power supply and 300nA unitary current, the neuron energy consumption is only 17fJ per synaptic event. The network occupies a 41,820μm 2 silicon area.
DOI:10.1109/NEWCAS.2017.8010091