A fast and low-power distance computation unit dedicated to neural networks, based on redundant arithmetic

This paper presents the design of a fast and low power consumption distance computation unit : /spl Sigma//sub i/(A/sub i/-B/sub i/)/sup 2/. It is dedicated to the digital RBF neural network implementation. The proposed architecture is composed of two parts. The first computes the distance (A/sub i/...

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Published inISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196) Vol. 4; pp. 878 - 881 vol. 4
Main Authors Dumonteix, Y., Bajot, Y., Mehrez, H.
Format Conference Proceeding
LanguageEnglish
Published IEEE 2001
Subjects
Arithmetic
Computer architecture
Computer networks
Delay
Electronic mail
Energy consumption
Laboratories
Neural networks
Neurons
Prototypes
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Summary:This paper presents the design of a fast and low power consumption distance computation unit : /spl Sigma//sub i/(A/sub i/-B/sub i/)/sup 2/. It is dedicated to the digital RBF neural network implementation. The proposed architecture is composed of two parts. The first computes the distance (A/sub i/-B/sub i/)/sup 2/, and the second performs the sum of these distances. It is based on an efficient squarer in redundant arithmetic. Thank to this operator, the distance measure circuits developed offer better performances than those based on classical arithmetic. The average gain is equal to 11% in delay and 18% in power consumption.
ISBN:9780780366855
0780366859
DOI:10.1109/ISCAS.2001.922378