Parallel architecture dedicated to connected component analysis

This paper presents the design of a dedicated parallel architecture for connected component analysis. Categorized in one-dimensional array processors, for an image of n/spl times/n pixels, the proposed architecture has n-1 linear processing elements (PEs), n/sup 2/ CAM memory modules, and a tree str...

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Bibliographic Details
Published inProceedings of 13th International Conference on Pattern Recognition Vol. 4; pp. 699 - 703 vol.4
Main Authors Mozef, E., Weber, S., Jaber, J., Tisserand, E.
Format Conference Proceeding
LanguageEnglish
Published IEEE 1996
Subjects
CADCAM
Communication switching
Computer aided manufacturing
Image analysis
Labeling
Parallel architectures
Pixel
Signal processing
Switches
Tree data structures
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Summary:This paper presents the design of a dedicated parallel architecture for connected component analysis. Categorized in one-dimensional array processors, for an image of n/spl times/n pixels, the proposed architecture has n-1 linear processing elements (PEs), n/sup 2/ CAM memory modules, and a tree structure of (n/2)-1 switches allowing communication through the global bus in O(log n) unit of propagation time. Well suited for low and intermediate-level vision, this architecture allows sequential processing through its line structure which is perfectly adapted to real time image analysis from any interlaced-mode video signal. This paper presents the algorithms for connected component labeling, area and perimeter determination, all of which are in O(n log n). The performance of the proposed architecture is compared with another architecture types. The simulation results, the possibility of implementation, and future work are discussed.
ISBN:9780818672828
081867282X
ISSN:1051-4651
DOI:10.1109/ICPR.1996.547655