A digital CMOS fully connected neural network with in-circuit learning capability and automatic identification of spurious attractors

Describes a completely connected feedback network with 64 binary neurons, using digital CMOS technology. The architecture implements a linear systolic loop, in which each neuron stores locally its own synaptic coefficients, and the potential calculation needs N time steps, each performing N partial...

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Bibliographic Details
Published inEuro ASIC '91 pp. 247 - 250
Main Authors Gascuel, J.-D., Weinfeld, M., Chakroun, S.
Format Conference Proceeding
LanguageEnglish
Published IEEE Comput. Soc. Press 1991
Subjects
Circuits
CMOS technology
Computer architecture
Convergence
Neural networks
Neurofeedback
Neurons
Routing
Signal design
Storage automation
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Summary:Describes a completely connected feedback network with 64 binary neurons, using digital CMOS technology. The architecture implements a linear systolic loop, in which each neuron stores locally its own synaptic coefficients, and the potential calculation needs N time steps, each performing N partial weighted sums, to realize the N/sup 2/ operations needed. It implements internal learning capabilities, using the Widrow-Hoff rule, which converges towards the pseudo-inverse rule by iteration, thus allowing partial correlation between prototypes, and a higher capacity, compared to the Hebb rule. Also, it implements an internal mechanism for detecting relaxations on spurious states. The average retrieval speed is about 20 mu s, whereas the learning time is approximately 15 to 30 ms for 15 moderately correlated prototypes.< >
ISBN:0818621850
9780818621857
DOI:10.1109/EUASIC.1991.212858