Design and implementation of error detection and correction circuitry for multilevel memory protection

• Published in: 32nd IEEE International Symposium on Multi-Valued Logic (ISMVL 2002) pp. 89 - 95
• Main Authors: Polianskikh, B., Zilic, Z.
• Format: Conference Proceeding Journal Article
• Language: English
• Published: Los Alamitos CA IEEE 2002
• Subjects: Applied sciences; Circuit faults; Computer errors; Computer science; control theory; systems; DRAM chips; Electronics; Error correction; Error correction codes; Exact sciences and technology; Hardware; Integrated circuits; Integrated circuits by function (including memories and processors); Mass production; Memory and file management (including protection and security); Memory organisation. Data processing; Protection; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Software; System-on-a-chip; Voltage; Storage capacity; Random access memory; Dynamical storage; Random access; Error detection; Error correcting code; Error correction; Storage access
• ISBN: 9780769514628; 0769514626
• ISSN: 0195-623X
• DOI: 10.1109/ISMVL.2002.1011075

Traditional memories use only two levels per cell (0/1), which limits their storage capacity to 1 bit per cell. By doubling the cell capacity, we increase the density of the memory at the expense of its reliability. There are several types of memories that employ multi-level techniques. The subject of this paper is the design of a multi-level dynamic random access memory (MLDRAM). The problem of its reliability is investigated and a practical solution is proposed. The solution is based on the organization of the error-correcting code (ECC) that is tuned to the MLDRAM implementation. Conventional memories employ single-error-correcting and double-error-detecting (SEC-DED) ECCs. While such codes have been considered for MLDRAMs, their use is inefficient, due to likely double-bit errors in a single cell. For this reason, we propose an induced ECC architecture that uses ECC in such a way that no common error corrupts two bits. Induced ECC allows a significant increase in the reliability of the MLDRAM, by making use of improved check-bit generation circuitry that allows us to use less space for the parity-bit generation circuitry. The suggested approach is able to correct a two-bit error in a two-bits-per-cell MLDRAM, which the basic ECC cannot correct. The proposed solutions make the MLDRAM more tolerant to any kind of fault, and consequently more practical for mass production.