System power distribution network theory and performance with various noise current stimuli including impacts on chip level timing

• Published in: 2009 IEEE Custom Integrated Circuits Conference pp. 621 - 628
• Main Authors: Smith, L., Shishuang Sun, Boyle, P., Krsnik, B.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.09.2009
• Subjects: Circuit noise; Network-on-a-chip; Noise level; Noise measurement; Power quality; Power systems; Resonance; System-on-a-chip; Timing; Voltage
• ISBN: 1424440718; 9781424440719
• ISSN: 0886-5930; 2152-3630
• DOI: 10.1109/CICC.2009.5280742

Power Quality has become a determining factor in product performance and reliability. The reactive portions of the power distribution network (PDN) have a greater effect on power quality than DC IR drop. Resonance in the parallel inductance and capacitance network creates an impedance peak in the frequency domain and undesirable voltage noise in the time domain. The on-chip voltage noise is usually much higher than PCB PDN noise. A method of determining and simulating circuit parameters and comparing results to a target impedance is presented. A test vehicle has been built and measured to provide laboratory measured results for PDN voltage noise. Switching current patterns are defined which generate typical and pathological voltage waveforms. PRBS patterns are used as a characterization technique to provide reasonable worst case resonance stimulation. The voltage noise is responsible for measured timing and jitter degradation in logic circuits.