Integrity of the gate oxide on the thin top Si layer in ITOX-SIMOX wafers

• Published in: 1999 IEEE International SOI Conference. Proceedings (Cat. No.99CH36345) pp. 119 - 120
• Main Authors: Nakashima, S., Kodate, J.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 1999
• Subjects: Current measurement; Design for quality; Diodes; Electric variables; Electric variables measurement; Fabrication; Oxidation; Plasma measurements; Thickness measurement; Voltage
• ISBN: 9780780354562; 0780354567
• ISSN: 1078-621X
• DOI: 10.1109/SOI.1999.819881

High-quality ITOX-SIMOX wafers have been used for the fabrication of 0.25 /spl mu/m fully depleted CMOS SIMOX LSIs with a 50 nm-thick active top Si layer (Ino et al, 1996). As the channel length gets much smaller, the top Si and the gate oxide must be thinner to suppress the short-channel effect (Su et al, 1993). It is very important to confirm the integrity of the gate oxide on a thinner top Si layer since the top Si adjacent to the top Si-buried oxide interface has a high density of small stacking fault complexes (SFC) (Jablonski et al, 1996). There have been few reports on this subject. Accordingly, we fabricated MOS diodes in ITOX-SIMOX wafers with a thinner top Si layer and investigated the electrical characteristics of the gate oxide grown on the wafers. The obtained results reveal that the gate oxide quality is high, and is comparable to the quality of the gate oxide of bulk wafers.