A high performance pMOSFET with two-step recessed SiGe-S/D structure for 32 nm node and beyond

• Published in: Solid-state electronics Vol. 51; no. 11; pp. 1437 - 1443
• Main Authors: Yasutake, Nobuaki, Azuma, Atsushi, Ishida, Tatsuya, Ohuchi, Kazuya, Aoki, Nobutoshi, Kusunoki, Naoki, Mori, Shinji, Mizushima, Ichiro, Morooka, Tetsu, Kawanaka, Shigeru, Toyoshima, Yoshiaki
• Format: Journal Article Conference Proceeding
• Language: English
• Published: Oxford Elsevier Ltd 01.11.2007; Elsevier Science
• Subjects: Applied sciences; Electronics; Exact sciences and technology; Mobility; MOSFET; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; SiGe-S/D; Strain; Transistors; Mobility; MOSFET; SiGe-S/D; Strain; Performance evaluation; Semiconductor alloys; High performance; Ge-Si alloys; Hole mobility; PMOS technology; Short channel; Optimization; Sodium; Drain current; Binary alloy; Damaging
• ISSN: 0038-1101; 1879-2405
• DOI: 10.1016/j.sse.2007.09.034

A novel SiGe-S/D structure for high performance pMOSFET called two-step recessed SiGe-source/drain (S/D) is developed with careful optimization of recessed SiGe-S/D structure. With this method, hole mobility, short channel effect and S/D resistance in pMOSFET are improved compared with conventional recessed SiGe-S/D structure. To enhance device performance such as drain current drivability, SiGe region has to be closer to channel region. Then, conventional deep SiGe-S/D region with carefully optimized shallow SiGe SDE region showed additional device performance improvement without SCE degradation. As a result, high performance 24 nm gate length pMOSFET was demonstrated with drive current of 451 μA/μm at ∣ V dd∣ of 0.9 V and I off of 100 nA/μm (552 μA/μm at ∣ V dd∣ of 1.0 V). Furthermore, by combining with V dd scaling, we indicate the extendability of two-step recessed SiGe-S/D structure down to 15 nm node generation.