Lithography independent high accuracy fabrication and characterization of next generation Nano-MOS-transistors with L = 25 nm and W = 75 nm

• Published in: Microelectronic engineering Vol. 84; no. 5; pp. 1484 - 1487
• Main Authors: Kallis, K.T., Horstmann, J.T., Fiedler, H.L.
• Format: Journal Article Conference Proceeding
• Language: English
• Published: Amsterdam Elsevier B.V 01.05.2007; Elsevier Science
• Subjects: Applied sciences; CMOS-process; Electronics; Exact sciences and technology; Integrated circuits; Integrated circuits by function (including memories and processors); Lithography; Microelectronic fabrication (materials and surfaces technology); Molecular electronics, nanoelectronics; MOS-transistor; Nanostructure; Quantum-effects; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Sub-50 nm-dimensions; Transistors; Sub-50 nm-dimensions; Nanostructure; MOS-transistor; CMOS-process; Lithography; Quantum-effects; Transistor gate; Quantum effect; HTTP; Nanoelectronics; Microelectronic fabrication; Manufacturing process; Complementary MOS technology; Development cost; Integrated circuit; MOS transistor; Modem; Custom circuit
• ISSN: 0167-9317; 1873-5568
• DOI: 10.1016/j.mee.2007.01.224

“The club of people who can afford an extreme sub-micron ASIC or COTS design is getting pretty exclusive” [Ron Wilson, EE Times – Platform Chips a Key, May 2000, <http://www.eetimes.com>]. This statement describes appropriately the problem of modern manufacturing processes. The 2005 International Technology Roadmap for Semiconductors predicts a minimum printed MOS-transistor gate length of 9 nm for the year 2020, which results in an effective channel length of only 6 nm [Semic. Ind. Asso., International Technology Roadmap for Semiconductors, 2005, <http://public.itrs.net>]. The necessity to invent solutions to achieve these goals is just one problem. The costs of process development, especially the mask costs have to remain economical. In this paper the fabrication of extremely small MOS-transistors with a minimum printed gate length of 25 nm and a width of 75 nm as they are prognosticated for the near term future (2012/2013) by the ITRS with extreme low demands to the used lithography (>1 μm) is described.